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lm3485 www.ti.com snvs178f ? may 2004 ? revised september 2009 lm3485 hysteretic pfet buck controller check for samples: lm3485 1 features applications 2 ? easy to use control methodology ? set-top box ? no control loop compensation required ? dsl/cable modem ? 4.5v to 35v wide input range ? pc/ia ? 1.242v to v in adjustable output range ? auto pc ? high efficiency 93% ? tft monitor ? 1.3% ( 2% over temp) internal reference ? battery powered portable applications ? 100% duty cycle ? distributed power systems ? maximum operating frequency > 1mhz ? always on power ? current limit protection ? msop-8 description the lm3485 is a high efficiency pfet switching regulator controller that can be used to quickly and easily develop a small, low cost, switching buck regulator for a wide range of applications. the hysteretic control architecture provides for simple design without any control loop stability concerns using a wide variety of external components. the pfet architecture also allows for low component count as well as ultra-low dropout, 100% duty cycle operation. another benefit is high efficiency operation at light loads without an increase in output ripple. current limit protection is provided by measuring the voltage across the pfet ? s r ds(on) , thus eliminating the need for a sense resistor. the cycle-by-cycle current limit can be adjusted with a single resistor, ensuring safe operation over a range of output currents. typical application circuit connection diagram figure 1. 8 lead plastic msop-8 top view 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2004 ? 2009, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
lm3485 snvs178f ? may 2004 ? revised september 2009 www.ti.com pin functions pin descriptions pin name pin number description isense 1 the current sense input pin. this pin should be connected to drain node of the external pfet. gnd 2 signal ground. nc 3 no connection. fb 4 the feedback input. connect the fb to a resistor voltage divider between the output and gnd for an adjustable output voltage. adj 5 current limit threshold adjustment. it connects to an internal 5.5 a current source. a resistor is connected between this pin and the input power supply. the voltage across this resistor is compared with the v ds of the external pfet to determine if an over-current condition has occurred. pwr gnd 6 power ground. pgate 7 gate drive output for the external pfet. pgate swings between v in and v in -5v. vin 8 power supply input pin. these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. absolute maximum ratings (1) vin voltage ? 0.3v to 36v pgate voltage ? 0.3v to 36v fb voltage ? 0.3v to 5v isense voltage ? 1.0v to 36v adj voltage ? 0.3v to 36v maximum junction temp. 150 c power dissipation 417mw @ t a = 25 c esd susceptibilty human body model (2) 2kv lead temperature vapor phase (60 sec.) 215 c infared (15 sec.) 220 c storage temperature ? 65 c to 150 c (1) absolute maximum ratings are limits beyond which damage to the device may occur. operating ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be guaranteed. for guaranteed specifications and test conditions, see the electrical characteristics. (2) the human body model is a 100 pf capacitor discharged through a 1.5k resistor into each pin. operating ratings (1) supply voltage 4.5v to 35v operating junction temperature ? 40 c to +125 c (1) absolute maximum ratings are limits beyond which damage to the device may occur. operating ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be guaranteed. for guaranteed specifications and test conditions, see the electrical characteristics. 2 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder links: lm3485
lm3485 www.ti.com snvs178f ? may 2004 ? revised september 2009 electrical characteristics specifications in standard type face are for t j = 25 c, and in bold type face apply over the full operating temperature range (t j = ? 40 c to +125 c). unless otherwise specified, v in = 12v, v isns = v in ? 1v, and v adj = v in ? 1.1v. datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. min typ max symbol parameter conditions unit (1) (2) (1) i q quiescent current at ground fb = 1.5v 250 400 a pin (not switching) v fb feedback voltage 1.226 1.242 1.258 v (3) 1.217 1.267 v hyst comparator hysteresis 10 15 mv 14 20 v cl (4) current limit comparator trip r adj = 20k ? 110 mv voltage r adj = 160k ? 880 v cl_offset current limit comparator v fb = 1.5v ? 20 0 +20 mv offset i cl_adj current limit adj current v fb = 1.5v 3.0 5.5 7.0 a source t cl current limit one shot off v adj = 11.5v 6 9 14 s time v isns = 11.0v v fb = 1.0v r pgate driver resistance source 5.5 ? i source = 100ma sink 8.5 i sink = 100ma i pgate driver output current source 0.44 a v in = 7v, p gate = 3.5v sink 0.32 v in = 7v, p gate = 3.5v i fb fb pin bias current v fb = 1.0v 300 750 na (5) t onmin_nor minimum on time in normal v isns = v adj +0.1v c load on 100 ns operation out = 1000pf (6) t onmin_cl minimum on time in current v isns = v adj +0.1v 175 ns limit v fb = 1.0v c load on out = 1000pf (6) %v fb / v in feedback voltage line 4.5 v in 35v 0.010 %/v regulation (1) all limits are guaranteed at room temperature (standard type face) and at temperature extremes (bold type face) . all room temperature limits are 100% tested. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods. all limits are used to calculate average outgoing quality level (aoql). (2) typical numbers are at 25 c and represent the most likely norm. (3) the v fb is the trip voltage at the fb pin when pgate switches from high to low. (4) v cl = i cl_adj * r adj (5) bias current flows out from the fb pin. (6) a 1000pf capacitor is connected between v in and pgate. copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 3 product folder links: lm3485
lm3485 snvs178f ? may 2004 ? revised september 2009 www.ti.com typical performance characteristics unless otherwise specified, t j = 25 c quiescent current vs feedback voltage input voltage vs (fb = 1.5v) temperature hysteresis voltage hysteresis voltage vs vs input voltage temperature current limit adj current current limit one shot off time vs vs. temperature temperature 4 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder links: lm3485 -40 junction temperature ( q c) adj current ( p a) v in =4.5v v in =12v v in =35v -20 0 20 40 60 80 100 120 140 4.5 5.0 5.5 6.0 6.5 8 9 10 11 one shot off time ( p s) 12 -40 -20 0 20 40 60 80 100 120 140 v in = 12v v in = 4.5v junction temperature (c) 90 95 100 105 110 4 12 20 28 36 input voltage (v) hysteresis voltage (%) t j = 25 q c -40 -20 0 20 40 60 80 100 120 140 4 6 8 10 12 14 hysteresis voltage (mv) junction temperature (c) v in =4.5v v in =35v fb voltage (v) junction temperature (c) v in =12v -40 -20 0 20 40 60 80 100 120 140 1.225 1.240 1.235 1.230 1.245 1.250 1.255 100 150 200 250 300 350 400 4 12 20 28 36 input voltage (v) quiescent current ( p a) t j = -40 q c t j = 25 q c t j = 125 q c
lm3485 www.ti.com snvs178f ? may 2004 ? revised september 2009 typical performance characteristics (continued) unless otherwise specified, t j = 25 c typical v pgate pgate voltage vs vs time input voltage v in = 9v minimum on time operating on time vs vs. output load current temperature (v in = 4.5v) efficiency operating on time vs vs output load current load current (v in = 12v) (v out = 3.3v, l = 6.8 h) copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 5 product folder links: lm3485 minimum on time (ns) v in = 4.5v v in = 12v v in = 24v 0 20 40 60 80 100 120 140 160 -20 -40 0 20 40 60 80 100 120 140 junction temperature (c) 0 2 4 6 8 10 v pgate (v) 0 50 100 150 t (ns) c pgate = 540 pf c pgate = 1020 pf c pgate = 110 pf c pgate = 1800 pf 4 12 20 28 36 3.0 3.5 4.0 5.0 5.5 input voltage (v) input voltage - pgate voltage (v) t j =125 q c t j = 25 q c t j = -40 q c 4.5 6.0 output load current (ma) operating on time ( p s) 3.3v out 1.242v out 5.0v out 0 1 2 3 4 5 0 200 400 600 800 1000 load current (ma) efficiency (%) v in = 12v v in = 4.5v 40 50 60 70 80 90 100 10 100 1000 10000 output load current (ma) operating on time ( p s) 3.3v out 1.242v out 0 200 400 600 800 1000 0 4 8 12 16 20
lm3485 snvs178f ? may 2004 ? revised september 2009 www.ti.com typical performance characteristics (continued) unless otherwise specified, t j = 25 c efficiency efficiency vs vs load current load current (v out = 3.3v, l = 22 h) (v out = 5.0v, l = 22 h) continuous mode operation start up (v in = 12v, v out = 3.3 v, i out = 500ma, l = 22 h) operating frequency vs discontinuous mode operation input voltage (v in = 12v, v out =3.3 v, i out = 50ma, l = 22 h) (v out = 3.3v, i out = 1a, c out(esr) = 80m ? , c ff = 100pf) 6 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder links: lm3485 0 200 400 600 800 4 12 20 28 36 input voltage (v) operating frequency (khz) l=10 p h l=15 p h l=22 p h inductor current sw node voltage output ripple voltage time (5 p s/div) 0a 0.5a 0v 5v 10v 0mv 20mv -20mv 0a 0.5a 0v 5v 10v 0mv 20mv -20mv 1a inductor current sw node voltage output ripple voltage time (2 p s/div) (1a/div) (2v/div) lind@c adj = 10nf lind@c adj = 1nf v out @c adj = 10nf v out @c adj = 1nf (2v/div) v in (10v/div) time (100 p s/div) 40 50 60 70 80 90 100 10 100 1000 10000 load current (ma) efficiency (%) v in = 12v v in = 24v efficiency (%) 40 50 60 70 80 90 100 load current (ma) 10 100 1000 10000 v in = 12v v in = 4.5v v in = 24v
lm3485 www.ti.com snvs178f ? may 2004 ? revised september 2009 typical performance characteristics (continued) unless otherwise specified, t j = 25 c output ripple voltage vs operating frequency vs input voltage output load current (v out = 3.3v, i out = 1a, c out(esr) = 80m ? , c ff = 100pf) (l = 22 h, c out(esr) = 45m ? , c ff = 100pf) feed-forward capacitor (cff) effect (v out = 3.3v, l = 22 h, i out = 500ma) block diagram copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 7 product folder links: lm3485 400 output current load (ma) operating frequency (khz) 12v in / 3.3v out 4.5v in / 1.242v out 12v in / 1.242v out 4.5v in / 3.3v out 12v in / 5.0v out 300 200 100 0 200 0 400 600 800 1000 input voltage (v) operating frequency (khz) output ripple voltage (mv) 0 50 100 150 200 250 300 4 12 20 28 36 0 50 100 150 200 250 300 @cff=100p @no cff @no cff @cff=100p ripple voltage operating frequency 0 20 40 60 80 4 12 20 28 36 input voltage (v) output ripple voltage (mv) l=10 p h l=15 p h l=22 p h
lm3485 snvs178f ? may 2004 ? revised september 2009 www.ti.com functional description overview the lm3485 is buck (step-down) dc-dc controller that uses a hysteretic control scheme. the comparator is designed with approximately 10mv of hysteresis. in response to the voltage at the fb pin, the gate drive (pgate pin) turns the external pfet on or off. when the inductor current is too high, the current limit protection circuit engages and turns the pfet off for approximately 9 s. hysteretic control does not require an internal oscillator. switching frequency depends on the external components and operating conditions. operating frequency reduces at light loads resulting in excellent efficiency compared to other architectures. 2 external resistors can easily program the output voltage. the output can be set in a wide range from 1.242v (typical) to v in . hysteretic control circuit the lm3485 uses a comparator based voltage control loop. the feedback is compared to a 1.242v reference and a 10mv hysteresis is designed into the comparator to ensure noise free operation. when the fb input to the comparator falls below the reference voltage, the output of the comparator moves to a low state. this results in the driver output, pgate, pulling the gate of the pfet low and turning on the pfet. with the pfet on, the input supply charges cout and supplies current to the load via the series path through the pfet and the inductor. current through the inductor ramps up linearly and the output voltage increases. as the fb voltage reaches the upper threshold, which is the internal reference voltage plus 10mv, the output of the comparator changes from low to high, and the pgate responds by turning the pfet off. as the pfet turns off, the inductor voltage reverses, the catch diode turns on, and the current through the inductor ramps down. then, as the output voltage reaches the internal reference voltage again, the next cycle starts. the lm3485 operates in discontinuous conduction mode at light load current or continuous conduction mode at heavy load current. in discontinuous conduction mode, current through the inductor starts at zero and ramps up to the peak, then ramps down to zero. next cycle starts when the fb voltage reaches the internal voltage. until then, the inductor current remains zero. operating frequency is lower and switching losses reduce. in continuous conduction mode, current always flows through the inductor and never ramps down to zero. the output voltage (v out ) can be programmed by 2 external resistors. it can be calculated as follows: v out = 1.242* ( r1 + r2 ) / r2 (1) figure 2. hysteretic window the minimum output voltage ripple (v out_pp ) can be calculated in the same way. v out_pp = v hyst ( r1 + r2 ) / r2 (2) for example, with v out set to 3.3v, v out_pp is 26.6mv v out_pp = 0.01* ( 33k + 20k ) / 20k = 0.0266v (3) 8 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder links: lm3485
lm3485 www.ti.com snvs178f ? may 2004 ? revised september 2009 operating frequency (f) is determined by knowing the input voltage, output voltage, inductor, v hyst , esr (equivalent series resistance) of output capacitor, and the delay. it can be approximately calculated using the formula: (4) where: : ( r1 + r2 ) / r2 delay: it includes the lm3485 propagation delay time and the pfet delay time. the propagation delay is 90ns typically. (see the propagation delay curve below.) figure 3. propagation delay the operating frequency and output ripple voltage can also be significantly influenced by the speed up capacitor (cff). cff is connected in parallel with the high side feedback resistor, r1. the location of this capacitor is similar to where a feed forward capacitor would be located in a pwm control scheme. however it's effect on hysteretic operation is much different. the output ripple causes a current to be sourced or sunk through this capacitor. this current is essentially a square wave. since the input to the feedback pin, fb, is a high impedance node, the current flows through r2. the end result is a reduction in output ripple and an increase in operating frequency. when adding cff, calculate the formula above with = 1. the value of cff depend on the desired operating frequency and the value of r2. a good starting point is 470pf ceramic at 100khz decreasing linearly with increased operating frequency. also note that as the output voltage is programmed below 2.5v, the effect of cff will decrease significantly. current limit operation the lm3485 has a cycle-by-cycle current limit. current limit is sensed across the v ds of the pfet or across an additional sense resistor. when current limit is activated, the lm3485 turns off the external pfet for a period of 9 s(typical). the current limit is adjusted by an external resistor, r adj . the current limit circuit is composed of the isense comparator and the one-shot pulse generator. the positive input of the isense comparator is the adj pin. an internal 5.5 a current sink creates a voltage across the external r adj resistor. this voltage is compared to the voltage across the pfet or sense resistor. the adj voltage can be calculated as follows: v adj = v in ? (r adj * 3.0 a) (5) where 3.0 a is the minimum i cl-adj value. the negative input of the isense comparator is the isense pin that should be connected to the drain of the external pfet. the inductor current is determined by sensing the v ds . it can be calculated as follows. v isense = v in ? (r dson * i ind_peak ) = v in ? v ds (6) copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 9 product folder links: lm3485 input voltage - output voltage (v) propogation delay (ns) 0 20 40 60 80 100 120 140 0 5 10 15 20 25 30 35 l=10 p h l=4.7 p h l=22 p h
lm3485 snvs178f ? may 2004 ? revised september 2009 www.ti.com figure 4. current sensing by v ds the current limit is activated when the voltage at the adj pin exceeds the voltage at the i sense pin. the isense comparator triggers the 9 s one shot pulse generator forcing the driver to turn the pfet off. the driver turns the pfet back on after 9 s. if the current has not reduced below the set threshold, the cycle will repeat continuously. a filter capacitor, c adj , should be placed as shown in figure 4 . c adj filters unwanted noise so that the isense comparator will not be accidentally triggered. a value of 100pf to 1nf is recommended in most applications. higher values can be used to create a soft-start function (see start up section). the current limit comparator has approximately 100ns of blanking time. this ensures that the pfet is fully on when the current is sensed. however, under extreme conditions such as cold temperature, some pfets may not fully turn on within the blanking time. in this case, the current limit threshold must be increased. if the current limit function is used, the on time must be greater than 100ns. under low duty cycle operation, the maximum operating frequency will be limited by this minimum on time. during current limit operation, the output voltage will drop significantly as will operating frequency. as the load current is reduced, the output will return to the programmed voltage. however, there is a current limit fold back phenomenon inherent in this current limit architecture. see figure 5 . figure 5. current limit fold back phenomenon at high input voltages ( > 28v) increased undershoot at the switch node can cause an increase in the current limit threshold. to avoid this problem, a low vf schottky catch diode must be used (see catch diode selection). additionally, a resistor can be placed between the isense pin and the switch node. any value up to approximately 600 ? is recommended. start up the current limit circuit is active during start-up. during start-up the pfet will stay on until either the current limit or the feedback comparator is tripped if the current limit comparator is tripped first then the fold back characteristic should be taken into account. start- up into full load may require a higher current limit set point or the load must be applied after start-up. one problem with selecting a higher current limit is inrush current during start-up. increasing the capacitance (c adj ) in parallel with r adj results in soft-start. c adj and r adj create an rc time constant forcing current limit to activate at a lower current. the output voltage will ramp more slowly when using the soft-start functionality. there are example start-up plots for c adj equal to 1nf and 10nf in the typical performance characteristics. lower values for c adj will have little to no effect on soft-start. 10 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder links: lm3485
lm3485 www.ti.com snvs178f ? may 2004 ? revised september 2009 external sense resistor the v ds of a pfet will tend to vary significantly over temperature. this will result an equivalent variation in current limit. to improve current limit accuracy an external sense resistor can be connected from v in to the source of the pfet, as shown in figure 6 . figure 6. current sensing by external resistor pgate when switching, the pgate pin swings from vin (off) to some voltage below vin (on). how far the pgate will swing depends on several factors including the capacitance, on time, and input voltage. as shown in the typical performance characteristics, pgate voltage swing will increase with decreasing gate capacitance. although pgate voltage will typically be around vin-5v, with every small gate capacitances, this value can increase to a typical maximum of vin-8.3v. additionally, pgate swing voltage will increase as on time increases. during long on times, such as when operating at 100% duty cycle, the pgate voltage will eventually fall to its maximum voltage of vin-8.3v (typical) regardless of the pfet gate capacitance. the pgate voltage will not fall below 0.4v (typical). therefore, when the input voltage falls below approximately 9v, the pgate swing voltage range will be reduced. at an input voltage of 7v, for instance, pgate will swing from 7v to a minimum of 0.4v. design information hysteretic control is a simple control scheme. however the operating frequency and other performance characteristics highly depend on external conditions and components. if either the inductance, output capacitance, esr, v in , or cff is changed, there will be a change in the operating frequency and output ripple. the best approach is to determine what operating frequency is desirable in the application and then begin with the selection of the inductor and c out esr. inductor selection (l1) the important parameters for the inductor are the inductance and the current rating. the lm3485 operates over a wide frequency range and can use a wide range of inductance values. a good rule of thumb is to use the equations used for national's simple switchers ? . the equation for inductor ripple ( i) as a function of output current (i out ) is: for i out < 2.0amps i i out * 0.386827 * i out ? 0.366726 for i out > 2.0amps i i out * 0.3 the inductance can be calculated based upon the desired operating frequency where: (7) and copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 11 product folder links: lm3485 v in - v ds - v out l = ' i x d f
lm3485 snvs178f ? may 2004 ? revised september 2009 www.ti.com (8) where d is the duty cycle, v d is the diode forward voltage, and v ds is the voltgae drop across the pfet. the inductor should be rated to the following: ipk = (iout+ i/2)*1.1 (9) (10) the inductance value and the resulting ripple is one of the key parameters controlling operating frequency. the second is the esr. output capacitor selection (c out ) the esr of the output capacitor times the inductor ripple current is equal to the output ripple of the regulator. however, the v hyst sets the first order value of this ripple. as esr is increased with a given inductance, then operating frequency increases as well. if esr is reduced then the operating frequency reduces. the use of ceramic capacitors has become a common desire of many power supply designers. however, ceramic capacitors have a very low esr resulting in a 90 phase shift of the output voltage ripple. this results in low operating frequency and increased output ripple. to fix this problem a low value resistor should be added in series with the ceramic output capacitor. although counter intuitive, this combination of a ceramic capacitor and external series resistance provide highly accurate control over the output voltage ripple. the other types capacitor, such as sanyo pos cap and os-con, panasonic sp cap, nichicon "na" series, are also recommended and may be used without additional series resistance. for all practical purposes, any type of output capacitor may be used with proper circuit verification. input capacitor selection (c in ) a bypass capacitor is required between the input source and ground. it must be located near the source pin of the external pfet. the input capacitor prevents large voltage transients at the input and provides the instantaneous current when the pfet turns on. the important parameters for the input capacitor are the voltage rating and the rms current rating. follow the manufacturer's recommended voltage derating. for high input voltage application, low esr electrolytic capacitor, the nichicon "ud" series or the panasonic "fk" series, is available. the rms current in the input capacitor can be calculated. (11) the input capacitor power dissipation can be calculated as follows. p d(cin) = i rms_cin 2 * esr cin (12) the input capacitor must be able to handle the rms current and the p d . several input capacitors may be connected in parallel to handle large rms currents. in some cases it may be much cheaper to use multiple electrolytic capacitors than a single low esr, high performance capacitor such as os-con or tantalum. the capacitance value should be selected such that the ripple voltage created by the charge and discharge of the capacitance is less than 10% of the total ripple across the capacitor. programming the current limit (r adj ) the current limit is determined by connecting a resistor (r adj ) between input voltage and the adj pin. r adj = i ind_peak * r dson /i cl_adj (13) where: r dson : drain-source on resistance of the external pfet i cl_adj : 3.0 a minimum i ind_peak = i load + i ripple /2 12 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder links: lm3485 i rms_cin = i out * (v out * (v in - v out )) 1/2 v in ' i 2 3 iout 2 + i rms = v in - v ds + v d v out + v d d =
lm3485 www.ti.com snvs178f ? may 2004 ? revised september 2009 using the minimum value for i cl_adj (3.0 a) ensures that the current limit threshold will be set higher than the peak inductor current. the r adj value must be selected to ensure that the voltage at the adj pin does not fall below 3.5v. with this in mind, r adj_max = (v in -3.5)/7 a. if a larger r adj value is needed to set the desired current limit, either use a pfet with a lower r dson , or use a current sense resistor as shown in figure 6 . the current limit function can be disabled by connecting the adj pin to ground and isense to vin. catch diode selection (d1) the important parameters for the catch diode are the peak current, the peak reverse voltage, and the average power dissipation. the average current through the diode can be calculated as following. i d_ave = i out * (1 ? d) (14) the off state voltage across the catch diode is approximately equal to the input voltage. the peak reverse voltage rating must be greater than input voltage. in nearly all cases a schottky diode is recommended. in low output voltage applications a low forward voltage provides improved efficiency. for high temperature applications, diode leakage current may become significant and require a higher reverse voltage rating to achieve acceptable performance. p-channel mosfet selection (q1) the important parameters for the pfet are the maximum drain-source voltage (v ds ), the on resistance (r dson ), current rating, and the input capacitance. the voltage across the pfet when it is turned off is equal to the sum of the input voltage and the diode forward voltage. the v ds must be selected to provide some margin beyond the input voltage. pfet drain current, id, must be rated higher than the peak inductor current, i ind-peak . depending on operating conditions, the pgate voltage may fall as low as v in - 8.3v. therefore, a pfet must be selected with a v gs greater than the maximum pgate swing voltage. as input voltage desreases below 9v, pgate swing voltage may also decrease. at 5.0v input the pgate will swing from v in to v in - 4.6v. to ensure that the pfet turns on quickly and completely, a low threshold pfet should be used when the input voltage is less than 7v. however, pfet switching losses will increase as the v gs threshold decreases. therefore, whenever possible, a high threshold pfet should be selected. total power loss in the fet can be approximated using the following equation: pdswitch = r dson *i out 2 *d + f*i out *v in *(t on + t off )/2 (15) where: t on = fet turn on time t off = fet turn off time a value of 10ns to 20ns is typical for ton and toff. a pfet should be selected with a turn on rise time of less than 100ns. slower rise times will degrade efficiency, can cause false current limiting, and in extreme cases may cause abnormal spiking at the pgate pin. the r dson is used in determining the current limit resistor value, r adj . note that the r dson has a positive temperature coefficient. at 100 c, the r dson may be as much as 150% higher than the 25 c value. this increase in r dson must be considered it when determining r adj in wide temperature range applications. if the current limit is set based upon 25 c ratings, then false current limiting can occur at high temperature. keeping the gate capacitance below 2000pf is recommended to keep switching losses and transition times low. this will also help keep the pfet drive current low, which will improve efficiency and lower the power dissipation within the controller. as gate capacitance increases, operating frequency should be reduced and as gate capacitance decreases operating frequency can be increased. copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 13 product folder links: lm3485
lm3485 snvs178f ? may 2004 ? revised september 2009 www.ti.com pcb layout the pc board layout is very important in all switching regulator designs. poor layout can cause switching noise into the feedback signal and general emi problems. for minimal inductance, the wires indicated by heavy lines should be as wide and short as possible. keep the ground pin of the input capacitor as close as possible to the anode of the diode. this path carries a large ac current. the switching node, the node with the diode cathode, inductor, and fet drain, should be kept short. this node is one of the main sources for radiated emi since it is an ac voltage at the switching frequency. it is always good practice to use a ground plane in the design, particularly at high currents. the two ground pins, pwr gnd and gnd, should be connected by as short a trace as possible; they can be connected underneath the device. these pins are resistively connected internally by approximately 50 ? . the ground pins should be tied to the ground plane, or to a large ground trace in close proximity to both the fb divider and c out grounds. the gate pin of the external pfet should be located close to the pgate pin. however, if a very small fet is used, a resistor may be required between pgate and the gate of the fet to reduce high frequency ringing. since this resistor will slow the pfet's rise time, the current limit blanking time should be taken into consideration (see current limit operation). the feedback voltage signal line can be sensitive to noise. avoid inductive coupling to the inductor or the switching node, by keeping the fb trace away from these areas. figure 7. typical pcb layout schematic (3.3v output) figure 8. top layer 14 submit documentation feedback copyright ? 2004 ? 2009, texas instruments incorporated product folder links: lm3485
lm3485 www.ti.com snvs178f ? may 2004 ? revised september 2009 bottom layer figure 9. typical pcb layout (3.3v output) silk screen figure 10. typical pcb layout (3.3v output) c1: c in 22 f/35v eejl1vd226r (panasonic) c2: c out 100 f/6.3v 6tpc100m (sanyo) c3: c adj 1nf ceramic chip capacitor c4: c ff 100pf ceramic chip capacitor d1: 1a/40v mbrs140t3 (on semiconductor) l1: 22 h :qh66sn220m01l (murata) q1: fdc5614p (fairchild) r1: 33k ? chip resistor r2: 20k ? chip resistor r3: r adj 24k ? chip resistor copyright ? 2004 ? 2009, texas instruments incorporated submit documentation feedback 15 product folder links: lm3485
package option addendum www.ti.com 17-nov-2012 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) samples (requires login) lm3485mm active vssop dgk 8 1000 tbd cu snpb level-1-260c-unlim lm3485mm/nopb active vssop dgk 8 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim lm3485mmx active vssop dgk 8 3500 tbd cu snpb level-1-260c-unlim lm3485mmx/nopb active vssop dgk 8 3500 green (rohs & no sb/br) cu sn level-1-260c-unlim lm3485q1mm/nopb active vssop dgk 8 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim lm3485q1mmx/nopb active vssop dgk 8 3500 green (rohs & no sb/br) cu sn level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 17-nov-2012 addendum-page 2 other qualified versions of lm3485, lm3485-q1 : ? catalog: lm3485 ? automotive: lm3485-q1 note: qualified version definitions: ? catalog - ti's standard catalog product ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant lm3485mm vssop dgk 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 lm3485mm/nopb vssop dgk 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 lm3485mmx vssop dgk 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 lm3485mmx/nopb vssop dgk 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 lm3485q1mm/nopb vssop dgk 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 lm3485q1mmx/nopb vssop dgk 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 package materials information www.ti.com 17-nov-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) lm3485mm vssop dgk 8 1000 203.0 190.0 41.0 lm3485mm/nopb vssop dgk 8 1000 203.0 190.0 41.0 lm3485mmx vssop dgk 8 3500 349.0 337.0 45.0 lm3485mmx/nopb vssop dgk 8 3500 349.0 337.0 45.0 lm3485q1mm/nopb vssop dgk 8 1000 203.0 190.0 41.0 lm3485q1mmx/nopb vssop dgk 8 3500 349.0 337.0 45.0 package materials information www.ti.com 17-nov-2012 pack materials-page 2

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